1. Field of the Invention
The present invention generally relates to latchup suppression integrated circuits, and more particularly to providing latchup suppression in a gate-array ASIC environment.
2. Background of the Invention
As the internal structures in integrated circuits are getting smaller, it is getting more difficult to control the phenomenon known as “latchup.” Latchup occurs when a pnpn structure transitions from a low current high voltage state to a high current low voltage state through a negative resistance region (i.e., forming an S-Type I-V (current/voltage) characteristic). Latchup is an unwanted phenomenon in that it either completely destroys or severely impairs electronic components within an integrated circuit.
Latchup is typically understood as occurring within a pnpn structure, or silicon controlled rectifier (SCR) structure. Interestingly, pnpn structures may be both intentionally designed and unintentionally formed between structures. Hence, latchup conditions may occur within peripheral circuits or internal circuits, within one circuit (intra-circuit), or between multiple circuits (inter-circuit).
Latchup is typically initiated by an equivalent circuit of a cross-coupled pnp and npn transistor. With the base and collector regions being cross-coupled, current flows from one device leading to the initiation of the second device (“regenerative feedback”). These pnp and npn elements may be any diffusions or implanted regions of other circuit elements (e.g., p-channel MOSFETs, n-channel MOSFETs, resistors, etc.) or actual pnp and npn bipolar transistors. In CMOS, the pnpn structure may be formed with a p-diffusion in a n-well, and a n-diffusion in a p-substrate (“parasitic pnpn”). In this case, the well and substrate regions are inherently involved in the latchup current exchange between regions.
The condition for triggering a latchup is a function of the current gain of the pnp and npn transistors, and the resistance between the emitter and the base regions. This inherently involves the well and substrate regions. The likelihood or sensitivity of a particular pnpn structure to latchup is a function of spacings (e.g., base width of the npn and base width of the pnp), current gain of the transistors, substrate resistance and spacings, the well resistance and spacings, and isolation regions.
Latchup is a concern in both internal circuits and peripheral circuitry. Latchup may also occur as the result of interaction of the ESD device, the I/O off-chip driver, and adjacent circuitry initiated in the substrate from overshoot and undershoot phenomenon. These may be generated by CMOS off-chip driver circuitry, receiver networks, and electrostatic discharge (ESD) devices. In CMOS I/O circuitry, undershoot and overshoot may lead to injection in the substrate. Hence, both a p-channel MOSFET and an n-channel MOSFET may lead to substrate injection. Simultaneous switching of circuitry, where overshoot or undershoot injection occurs, leads to injection into the substrate which leads to both noise injection and latchup conditions. Supporting elements in these circuits, such as pass transistors, resistor elements, test functions, over voltage dielectric limiting circuitry, bleed resistors, keeper networks, and other elements may be present leading to injection into the substrate. ESD elements connected to the input pad may also lead to latchup. ESD elements that may lead to noise injection and latchup include MOSFETs, pnpn SCR ESD structures, p+/n-well diodes, n-well-to-substrate diodes, n+ diffusion diodes, and other ESD circuits. ESD circuits may contribute to noise injection into the substrate and latchup.
An additional process may occur by the interaction of “activated” and “unactivated” elements in a gate-array environment. In an ASIC environment, a “sea of gates” philosophy allows customization and personalization of circuit elements at a metalization level where the silicon regions are predefined. Unused n-diffusion regions are grounded, and unused p-diffusion regions are connected to VDD. Unfortunately, this implementation may lead to latchup. As the substrate voltage potential rises relative to the n-diffusion, all the elements of the gate arrays tend to forward bias. As the substrate voltage potential lowers, the unused p-diffusion elements, the n-well and the substrate may activate the vertical pnp. This may occur as a result of minority carrier injection in wells and substrate regions.
In an ASIC gate array environment, it has been observed that as a negative pulse is injected into an input pad, ESD current discharge to the substrate may flow outside of the I/O cell region, leading to “turn-on” of the adjacent gate array regions connected to the VSS and VDD rails. This often results in increasing the likelihood of latchup and leading to failure of the latchup specification.
An additional problem in latchup is the propagation of the latchup process once latchup is initiated in an array environment. As an initial source injects electrons into the substrate, a first circuit element may latchup. The latchup of a first circuit leads to the turn-on of a pnp parasitic element leading to more injection into the substrate. As a result, the injection into the substrate of the primary initial perturbation is additive by linearity to the secondary injection initiated by the circuit undergoing latchup. This leads to an adjacent circuit to also latchup as the total current of the initial primary injection current (which decreases with distance from initial injection point) is additive to the secondary. This leads to a propagation run-away effect leading to additional latchup propagation. Hence, the solution of detachment of the rails is a structure to “truncate the latchup propagation” through the semiconductor chip and array region.
Latchup may be initiated by negative transient on the VDD which may lead to a forward biasing of all the n-diffusions and n-well structures and electron injection throughout the semiconductor chip substrate. This produces a “sea of electrons” injected in the chip substrate. Equivalently, a positive transient on the VSS may lead to hole injection and forward biasing of the substrate-well junction providing a “sea of holes” event. In this event, it is possible the metric of how far the detachment is placed may be dependent on other physical parameters, such as the latchup sensitivity of the gate array element, circuit type (e.g., SRAM cell, logic gate, gate array MOSFET) based on the parasitic current gains, substrate, and well resistances.
Latchup may occur from voltage or current pulses that occur on the power supply lines, such as VDD and VSS. Transient pulses on power rails (e.g., substrate or wells) may trigger latchup processes. The propagation of the impulse on the power grids may also be quantified and appropriate latchup control networks may be placed. Latchup may also occur from a stimulus to the well or substrate external to the region of the thyristor structure from minority carriers.
Latchup may be initiated from internal or external stimulus. Latchup is known to occur from single event upsets (SEU). Single event upsets may include terrestial emissions from nuclear processes, cosmic ray events, as well as events in space environments. Cosmic ray particles may include proton, and neutron, gamma events, as well as a number of particles that enter the earth atmosphere. Terrestial emissions from radioactive events, such as alpha particles, and other radioactive decay emissions, may also lead to latchup in semiconductors. In this case, it is possible that the methodology is applied to sensitive gate array circuits, as well as other circuits, such as pass transistors and SRAM cells. As applied to the gate array circuits, the SRAM power rails and ground rails may be decoupled to avoid latchup or SEU events. In this case, the methodology may be addressed by certain functional blocks instead of spatial dependence. Hence the methodology of detachment and connection to the latchup control networks may be according to the circuit type as well as physical localness (placement) to the injection source.